1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which data is transferred between circuit blocks having different power supply voltage and clock frequency.
2. Description of the Related Art
With recent semiconductor integrated circuit design, manufacturing a circuit to have high performance and low power consumption is a significant concern. According to a lower power circuit configuration method, a semiconductor integrated circuit is divided into a plurality of circuit blocks differing from one another in power supply voltage and clock frequency so as to optimize performance and power consumption of the semiconductor integrated circuit. The above method has a problem in that transferring data between circuit blocks differing in clock frequency is necessary. Furthermore, clock skew between the circuit blocks differing in clock frequency is also a problem. To resolve these problems, a ‘globally asynchronous locally synchronous (GALS) method’ of connecting the circuit blocks differing in clock frequency via an asynchronous bus is proposed.
In general, an asynchronous bus connecting first and second circuit blocks differing from each other in clock frequency includes a data transfer circuit for transferring data therebetween. More specifically, a data signal transferred from the first circuit block is transferred to the data transfer circuit in synchronization with a first clock frequency set to the first circuit block. The data signal transferred to the data transfer circuit is transferred to the second circuit block in synchronization with a second clock frequency set to the second circuit block. When the data signal is transferred to the second circuit block, the second circuit block transfers, to the first circuit block via the data transfer circuit, a reply signal indicating that the data signal has been transferred.
A data transfer path from the first circuit block to the second circuit block, through which the data signal is transferred, and a path from the second circuit block to the first circuit block, through which the reply signal is transferred, are hereafter referred to as a ‘transfer loop’.
Throughput of data transfer via the data transfer circuit is dependent on the duration time that the data signal and the reply signal transfer through the transfer loop. In other words, if the transfer loop is long, data transfer time via the data transfer circuit increases, thereby decreasing the throughput. If the transfer loop is short, throughput of data transfer via the data transfer circuit improves. Accordingly, shortening the transfer loop is important for improving performance of a semiconductor integrated circuit having a plurality of circuit blocks that differ in clock frequency.
Generally, signal levels of the circuit blocks differ between circuit blocks that differ in power supply voltage. Therefore, when the power supply voltage for a first circuit block differs from the power supply voltage for a second circuit block, a level converter for converting the level of the data signal from an internal signal level of the first circuit block to an internal signal level of the second circuit block, and a level converter for converting the level of the reply signal from the internal signal level of the second circuit block to the internal signal level of the first circuit block are required to be provided within the transfer loop. As a result, the transfer loop becomes longer, and the data transfer throughput decreases. In other words, impaired performance of the semiconductor integrated circuit occurs.